Search results

Discusses the many variables and problems associated with the process--from sample removal to micro-etch-- and the variables common to high volume microsection. The process variables and problems are organized so that the reader can research a specific issue or overview the variables of a process area. 31 pages. Released October 1993.

Dubbed the "nightmare microsection," this full-color, 24x36-inch (60 x 90 cm) wall poster identifies 42 phenomena that can be seen in cross-sections of plated-through holes. Outstanding visual for supporting discussions of common (and not so common) phenomena. All defects are labeled and match the language used in IPC standards IPC-A-600, IPC-6012 and IPC-T-50. Use this poster as a tool to assist...

IPC-9631 addresses concerns and considerations related to IPC-TM-650, Method 2.6.27, Thermal Stress, Convection Reflow Assembly Simulation. This document describes how the test method is intended for use and the rationale behind some of the protocols and requirements. This document was developed with the understanding that the test method will require special equipment and the proper set-up and...

Published jointly with the Japan Printed Circuits Association, IPC/JPCA-2315 provides an easy to follow tutorial on the selection of HDI and microvia design rules and structures. Addresses various considerations when designing an HDI printed wiring board including design examples and processes, selection of materials, general descriptions, and various microvia technologies. Offers designers and...

This guideline standard is intended to aid in interpretation of the requirements in IPC-9191, "General Guidelines for Implementation of Statistical process Control," specifically for printed board assembly (PBA) manufacture. This document and IPC-9191 should be used together; the standards are cross-referenced to each other in the Appendices of this guideline. This standard promotes process...

Implementing flip chip technology in a direct chip attach (DCA) assembly presents some unique challenges for design, assembly, inspection and repair personnel. IPC-7094 delivers useful and practical information to anyone who is currently using or contemplating developing products that employ the very complex and high density methods needed for the flip chip technology. The concepts have become...

As most of the world converts to lead-free manufacturing, the concern over tin whiskers as a reliability hazard has grown due to the emergence of pure tin as a dominate component surface finish. A significant amount of research on tin whisker formation and tin whisker mitigating strategies has been performed in both commercial and defense industries. This working paper is a summary of the...

This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and...

Covers the various conductive and dielectric materials that can be used for the fabrication of HDI and microvias. The 23 specification sheets included in IPC/JPCA-4104 cover the qualification and conformance requirements for such materials as photoimageable dielectric dry films and liquids, epoxy blends and coated foils. IPC/JPCA-4104 also includes six new test methods developed specifically for...

This standard establishes mechanical outline requirements for devices supplied in flip chip or Chip Size Package (CSP) formats, including die surface, die terminals, and interconnection balls/bumps/lands to the next level. 13 Pages. Released February 2003.

This test method defines the procedures for performing acoustic microscopy on non-hermetic encapsulated electronic components. It provides users with an acoustic microscopy process flow for detecting defects non-destructively in plastic packages while achieving reproducibility. Developed by IPC and JEDEC. 16 pages. Released April 1999. Equivalent to IEC Publicly Available Specification (PAS) 62191

This document establishes the requirements and interactions necessary for printed board assembly processes for interconnecting high performance/high pin count IC packages. Includes information on design principles, material selection, board fabrication, assembly technology, testing strategy and reliability expectations based on end-use environments. Developed by IPC, EIA, MCNC and Sematech. 96...

This handbook is an essential resource for anyone involved in manufacturing or purchasing PCBs. Hundreds of real-world, full-color photos spotlight more than 650 PCB process defects, with causes and corrective actions for each. IPC-9121 supersedes the PCB sections of IPC-PE-740A. Released March 2016

Cleaning of stencils and misprinted PCBs has taken an increasingly important role in surface mount technology. Fine and ultra-fine pitch lands, together with other advanced packages, place new demands on stencil cleaning. Paste volume is a critical issue for fine, ultra-fine, chip-scale, BGA and flip-chip components. Insufficient solder due to clogging of stencil apertures is a primary cause of...

This standard describes the design and assembly challenges for implementing Bottom Termination surface mount Components (BTCs) whose external connections consist of metallized terminals that are an integral part of the component body. The BTCs in this document include all types and forms of bottom-only termination components intended for surface mounting. This includes such industry descriptive...

The IPC-7091 intends to provide useful and practical information to those who are designing, developing or using 3D-packaged semiconductor components or those who are considering 3D package implementation. The 3D semiconductor package may include multiple die elements—some homogeneous and some heterogeneous. The package may also include several discrete passive SMT devices, some of which are...

This new standard supplements existing IPC-6010 series specifications with qualification and performance requirements for in-process and finished printed boards containing embedded passive circuitry (distributive capacitive planes and capacitive or resistive components). 10 pages. Released March 2009. Included in Collections C-105, C-1000 and the 6010 Series

The successor to the IPC-SM-782A is here! The document covers land pattern design for all types of passive and active components, including resistors, capacitors, MELFs, SSOPs, TSSOPs, QFPs, BGAs, QFNs and SONs. The standard provides many brand new features, including an intelligent land pattern naming convention, zero component rotations for CAD systems, and a set of three separate land pattern...

Track the substantive changes in IPC-6012D with this redline product. This is the D revision in its entirety, with each change highlighted on the page. Click the text to launch a pop-up with an explanation of the change from the C revision. Available for download only. IPC-6012D covers qualification and performance of rigid printed boards, including single-sided, double-sided, with or without...

This document describes the design and assembly challenges for implementing passive and active components, in either formed or placed methodology, into a printed board. It provides useful and practical information to decision makers of formed or placed, passive or active components and helps establish inspection techniques, testing processes, and reliability validations. Users will also learn...

Status of the technology discussion on the various methodologies for mounting and interconnecting active devices to a variety of substrate materials is summarized in this document. Reviews mounting techniques of tape automated bonding (TAB), chip on board (COB) and flip chip. Examinations of the most commonly used substrate options of laminate, ceramic and silicon are also reviewed. Editor: John...

The IPC-2231 standard provides guidelines for establishing a best practice methodology for use in developing a formal DFX (Design for Manufacturing, Fabrication, Assembly, Testability, Cost, Reliability, Environment, Reuse) process for layout of printed board assemblies that utilize surface mount and through hole devices.

IPC-1791 provides minimum requirements, policies and procedures for printed board design, fabricating and assembly organizations and/or companies to become trusted sources for markets requiring high levels of confidence in the integrity of delivered products. Demonstration of the ability to meet and maintain the requirements of IPC-1791 as trusted design, fabricator or assembly organization...

Manufacturers of high reliability electronics have been working for many years to mitigate the deleterious effects of tin whisker formation. One highly effective means to suppress the growth of tin whiskers is to replace the pure tin plating with reflowed tin-lead solder. One approach is to fully consume the tin plating by tin-lead solder during the SMT reflow process. This phenomenon of tin...